The present disclosure relates to a semiconductor integrated circuit, and more particularly, to a dummy cell array structure that may be used in a semiconductor integrated circuit including a fin field-effect transistor (FinFET) device.
A FinFET or a fin-type transistor is a three-dimensional transistor having a fin structure that protrudes from a substrate. As the entire surface of the protruded fin structure of the FinFET device may be used as a channel area, a sufficient channel length may be provided. Accordingly, a short channel effect may be prevented or reduced, and thus, for example, a current leakage problem in regard to a surface area, which is generated by a short channel effect in a planar type transistor according to the conventional art may be prevented.
As the high integration of semiconductor devices has recently been progressing fast, a layout design of the semiconductor integrated circuit may be time consuming and expensive. In general, a layout design technique based on a standard cell may be used to reduce the time and costs. In a layout design method based on a standard cell, devices such as logic OR gates or logic AND gates which are repeatedly used may be designed as standard cells in advance and stored in a computer system. Then, these standard cells are placed and wired where needed when making a layout design, thereby reducing the time for making the layout design. Typically, when the number of polygons of the layout design is reduced the time and costs may be reduced.